This application claims benefit of Korean Patent Application No. P2000-68113, filed on Nov. 16, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method for driving a nonvolatile ferroelectric memory device.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory device, i.e. ferroelectric random access memory (FRAM), has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this characteristic, the nonvolatile ferroelectric memory has been highly regarded as a next generation memory device.
As a memory device having structures similar to those of a DRAM, FRAM uses high residual polarization, which is a characteristic of ferroelectric material, by using ferroelectric material as a component of a capacitor.
Due to such characteristic of residual polarization, data remains unerased even if the electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric.
As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states) without being erased due to the presence of residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states to 1 and 0, respectively.
FIG. 2 illustrates a unit cell of a nonvolatile ferroelectric memory device of the related art.
As shown in FIG. 2, the nonvolatile ferroelectric memory device of the related art includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart at equal intervals from the wordline in the same direction as the wordline, a transistor T1 with a gate connected to the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1, whereof a first terminal is connected with a drain of a transistor T1 and a second terminal is connected with a plate line P/L.
The data input/output operation of such ferroelectric memory device is described as follows.
FIG. 3A is a timing chart illustrating the operation of the writing mode of the related art nonvolatile ferroelectric memory device, and FIG. 3B is a timing chart illustrating the operation of the reading mode thereof.
During the writing mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, the writing mode starts if a write enable signal is applied from high state to low state.
Subsequently, if address decoding in the writing mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WFBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value xe2x80x9c1xe2x80x9d is written on the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The reading operation of data stored in a cell is described as follows.
If an externally applied chip enable signal CSBpad is activated from high state to low state, all of the bitlines become equipotential to low voltage by an equalizer signal before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address enabling a corresponding cell to be selected.
The high signal is applied to the plate line of the selected cell to destroy data Qs corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory.
If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data Qs is not destroyed. The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In other words, as shown in the hysteresis loop of FIG. 1, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited on to an xe2x80x9cfxe2x80x9d state. If the data is not destroyed, the xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case the data is destroyed, while the logic value xe2x80x9c0xe2x80x9d is output in case the data is not destroyed.
As described above, after the sensing amplifier amplifies data, the plate line becomes inactive from a high state to a low state at the state whereby the high signal is applied to the corresponding wordline to recover the data from the original data.
The aforementioned method for driving a nonvolatile memory device of the related art encounters the following problems.
In case of the operation of the writing mode and the reading mode of data, the wordline should be activated from an active period of an operation cycle (1 cycle) to a pre-charge period. Thus, it is difficult to control the amount of charge released from a cell, and accordingly, it is difficult to read or write the data equally from the entire cell array.
In addition, the sensing amplifier is activated when the wordline is activated to a high state. This results in a difference between the capacitance of a main cell bitline and the capacitance of a reference cell bitline, and accordingly, there is a limitation in reducing the cell size by decreasing the sensing voltage.
Accordingly, the present invention is directed to a method for driving a nonvolatile ferroelectric memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for driving a nonvolatile ferroelectric memory device that enables the operation of the writing mode and the reading mode of data to be carried out equally in the entire cell array, without depending on its position. This is due to a controlled operation of a first wordline pulse width, which controls the amount of charge released from the cell.
Another object of the present invention is to provide a method for driving a nonvolatile ferroelectric memory device that suitable for reducing the cell size by decreasing the minimum sensing voltage. This is due to the equalized RC loading conditions of a main bitline and a reference bitline in view of the sensing amplifier, which is possible by activating the sensing amplifier after making the first wordline pulse inactive.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for driving a nonvolatile ferroelectric memory device includes a main cell and a reference cell provided with one transistor and one or more ferroelectric capacitors among a first voltage applying line (wordline), a bitline and a second voltage applying line, the method comprising the steps of primarily activating the wordline and a reference wordline at high level in an active period of one cycle, deactivating the wordline and the reference wordline, activating a sensing amplifier after the wordline is inactivated, secondarily activating the wordline at high level in a state that the sensing amplifier is activated in the active period, applying high level of at least one time or more to the second voltage applying line to be coincident with the secondary active period of the wordline at at least one point, and transiting a chip enable signal from low level to high level to precharge the chip enable signal.